library IEEE;
use IEEE.std_logic_1164.all;

entity input_buffer_tb is
end entity input_buffer_tb;

architecture structural of input_buffer_tb is
  
component input_buffer is
	port (	clk		: in	std_logic;

		sensor_l_in	: in	std_logic;
		sensor_m_in	: in	std_logic;
		sensor_r_in	: in	std_logic;

		sensor_l_out	: out	std_logic;
		sensor_m_out	: out	std_logic;
		sensor_r_out	: out	std_logic
	);
end component;

signal  clk, sensor_l_in, sensor_m_in, sensor_r_in, sensor_l_out, sensor_m_out, sensor_r_out  : std_logic;

begin
  clk         <=  '1' after 0 ns,
                  '0' after 10 ns when clk /= '0' else '1' after 10 ns;
  sensor_l_in <=  '0' after 0 ns,
                  '1' after 14 ns,
                  '0' after 31 ns,
						'1' after 58 ns,
                  '0' after 74 ns;
  sensor_m_in <=  '0' after 0 ns,
                  '1' after 24 ns,
                  '0' after 44 ns,
						'1' after 79 ns,
                  '0' after 94 ns;
  sensor_r_in <=  '0' after 0 ns,
                  '1' after 16 ns,
                  '0' after 37 ns,
						'1' after 83 ns,
                  '0' after 112 ns;
  
  lbl0: input_buffer PORT MAP ( clk, sensor_l_in, sensor_m_in, sensor_r_in, sensor_l_out, sensor_m_out, sensor_r_out);
    
end architecture structural;
